View A395006_1118739.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

A3950 DMOS Full-Bridge Motor Driver
Features and Benefits
Low RDS(on) outputs Overcurrent protection Motor lead short-to-supply protection Short-to-ground protection Sleep function Synchronous rectification Diagnostic output Internal undervoltage lockout (UVLO) Crossover-current protection
Description
Designed for PWM (pulse width modulated) control of dc motors, the A3950 is capable of peak output currents to 2.8 A and operating voltages to 36 V. PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied PWM control signals. Internal synchronous rectification control circuitry is provided to lower power dissipation during PWM operation. Internal circuit protection includes motor lead short-tosupply / short-to-ground, thermal shutdown with hysteresis, undervoltage monitoring of VBB and VCP, and crossover-current protection.
Package EU, 16 pin QFN with Exposed Thermal Pad
Packages:
Package LP, 16 pin TSSOP with Exposed Thermal Pad
The A3950 is supplied in a thin profile (<1.2 mm overall height) 16 pin TSSOP package (LP), and a very thin (0.75 mm nominal height) QFN package. Both packages provide an exposed pad for enhanced thermal dissipation, and are lead (Pb) free with 100% matte tin leadframe plating.
Approximate Scale 1:1
Typical Application Diagrams
VBB
0.1 F 50 V NFAULT GND CP2 CP1 OUTB SENSE OUTA VBB NC 0.1 F 50 V 100 F 50 V NC VREG VCP 0.1 F 50 V 0.22 F 25 V
0.22 F 25 V
VBB
NFAULT
MODE
VDD 5 k
PHASE GND SLEEP ENABLE
VREG
VCP
VDD 5 k
MODE PHASE GND SLEEP ENABLE OUTA SENSE
A3950 EU Package
A3950 LP Package
GND CP2 CP1 OUTB VBB 0.1 F 50 V 0.1 F 50 V 100 F 50 V
0.1 F 50 V
Package EU
Package LP
A3950DS, Rev. 4
A3950
DMOS Full-Bridge Motor Driver
Selection Guide
Part Number A3950SLP-T A3950SLPTR-T A3950SEU-T A3950SEUTR-T Packing 96 pieces / tube 13 in. reel, 4000 pieces / reel 92 pieces / tube 7 in. reel, 1500 pieces / reel Package 16 pin TSSOP with exposed thermal pad 16 pin QFN with exposed thermal pad
Absolute Maximum Ratings
Characteristic Load Supply Voltage Output Current Sense Voltage VBB to OUTx OUTx to SENSE Logic Input Voltage Operating Ambient Temperature Maximum Junction Temperature Storage Temperature VIN TA TJ(max) Tstg Range S Symbol VBB IOUT VSENSE Notes Rating 36 2.8 500 36 36 -0.3 to 7 -20 to 85 150 -40 to 125 Units V A mV V V V C C C
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
2
A3950
DMOS Full-Bridge Motor Driver
Functional Block Diagram
0.1 F
CP1
CP2
Charge Pump
VCP
0.1 F
VREG 0.22 F 25 V MODE
Low-Side Gate Supply Bias Supply
VBB
Load Supply
0.1 F
100 F
PHASE OUTA Control Logic VDD ENABLE 5 k SLEEP 5 k NFAULT
UVLO STB STG TSD Warning VBB OUTA OUTB SENSE
OUTB
SENSE
Motor Lead Protection
GND
Pad
GND
Terminal List Table Name NFAULT MODE PHASE GND SLEEP ENABLE OUTA SENSE VBB OUTB CP1 CP2 VCP VREG NC Pad Number EU 15 16 1 2, 12 3 4 6 7 8 9 10 11 13 14 5 - LP 1 2 3 4,13 5 6 7 8 9 10 11 12 14 15 16 - Description Fault output, open drain Logic input Logic input for direction control Ground Logic input Logic input DMOS full-bridge output A Power return Load supply voltage DMOS full-bridge output B Charge pump capacitor terminal Charge pump capacitor terminal Reservoir capacitor terminal Regulator decoupling terminal No connection Exposed pad for thermal dissipation connect to GND pins
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
3
A3950
DMOS Full-Bridge Motor Driver
1For
ELECTRICAL CHARACTERISTICS at TJ = 25C, VBB = 8 to 36 V, unless noted otherwise Characteristics Symbol Test Conditions fPWM < 50 kHz Motor Supply Current IBB Charge pump on, outputs disabled Sleep mode VIH PHASE, ENABLE, MODE Input Voltage VIL VIH SLEEP Input Voltage VIL IIH VIN = 2.0 V PHASE, MODE Input Current1 IIL VIN = 0.8 V VIN = 2.0 V IIH ENABLE Input Current IIL VIN = 0.8 V IIH VIN = 2.7 V SLEEP Input Current IIL VIN = 0.8 V NFAULT Output Voltage VOL Isink = 1.0 mA Input Hysteresis, except SLEEP VIHys Source driver, IOUT = -2.8 A, TJ=25C Source driver, IOUT = -2.8 A, TJ=125C Output On Resistance RDS(on) Sink driver, IOUT = 2.8 A, TJ=25C Sink driver, IOUT = 2.8 A, TJ=125C Source diode, If = -2.8 A Body Diode Forward Voltage1 Vf Sink diode, If = 2.8 A PWM, change to source or sink ON Propagation Delay Time tpd PWM, change to source or sink OFF Crossover Delay tCOD Protection Circuitry UVLO Threshold VUV VBB increasing UVLO Hysteresis VUVHys Overcurrent Threshold2 IOCP Overcurrent Protection Period tOCP Thermal Warning Temperature TJW Temperature increasing Thermal Warning Hysteresis TJWHys Recovery = TJW - TJWHys Thermal Shutdown Temperature TJTSD Temperature increasing Thermal Shutdown Hysteresis TJTSDHys Recovery = TJTSD - TJTSDHys
Min. Typ. Max. Units - 6 8.5 mA - 3 4.5 mA - - 10 A 2.0 - - V - - 0.8 V 2.7 - - V - - 0.8 V - <1.0 20 A -20 <-2.0 20 A - 40 100 A - 16 40 A - 27 50 A - <1 10 A - - 0.4 V 100 150 250 mV - 0.35 0.48 - 0.55 0.8 - 0.3 0.43 - 0.45 0.7 - - 1.4 V - - 1.4 V - 600 - ns - 100 - ns - 500 - ns - - 3 - - - - - 6.5 250 - 1.2 160 15 175 15 - - - - - - - - V mV A ms C C C C
2Overcurrent
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. protection is tested at 25C in a restricted range and guaranteed by characterization.
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Preliminary: EU package, 4-layer PCB based on JEDEC standard Package Thermal Resistance RJA LP package, 4-layer PCB based on JEDEC standard LP package, 2-layer PCB with 3.8 in.2 copper both sides, connected by thermal vias *Additional thermal data available on the Allegro Web site. Value 30 34 43 Units C/W C/W C/W
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
4
A3950
DMOS Full-Bridge Motor Driver
Timing Diagram: PWM Control
SLEEP ENABLE PHASE MODE
VBB
VOUTA 0
VBB VOUTB
0
IOUTX
0
A
1
2
3
4
5
6
7
8
9
VBB 15 6 OutA 3 24 OutB OutA 8
VBB
7 OutB
9
A Charge pump and VREG power-on delay (200 s)
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
5
A3950
DMOS Full-Bridge Motor Driver
Timing Diagram: Overcurrent Control
VOUTA VOUTB High-Z
IPEAK IOCP
IOUTx
ENABLE, Source or Sink BLANK
Charge Pump Counter
tBLANK tOCP
NFAULT Motor lead short condition Normal dc motor capacitance
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
6
A3950
DMOS Full-Bridge Motor Driver
Functional Description
Device Operation. The 3950 is designed to operate one dc motor. The currents in the output full-bridges, all N-channel DMOS, are regulated with fixed off-time pulse width modulated (PWM) control circuitry. Logic Inputs. If logic inputs are pulled up to VDD , it is good practice to use a high value pull-up resistor in order to limit current to the logic inputs should an overvoltage event occur. Logic inputs include: SLEEP, MODE, PHASE, and ENABLE. The voltage on any logic input cannot exceed the specified maximum of 7 V. VREG. This supply voltage is used to run the sink-side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. The VREG pin should be decoupled with a 0.22 F capacitor to ground. Charge Pump. The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1 F ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1 F ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the high-side DMOS devices. The VCP voltage level is internally monitored and, in the case of a fault condition, the outputs of the device are disabled. Shutdown. In the event of a fault due to excessive junction temperature, or low voltage on VCP or VREG, the outputs of the device are disabled until the fault condition is removed. At power-on the UVLO circuit disables the drivers. Sleep Mode. Control input SLEEP is used to minimize power consumption when the A3950 is not in use. This disables much
Control Logic Table1 Pin PHASE 1 0 X 1 0 X
1X 2To
of the internal circuitry, including the regulator and charge pump. A logic low setting puts the device into Sleep mode, and a logic high setting allows normal operation. After coming out of Sleep mode, provide a 1 ms interval before applying PWM signals, to allow the charge pump to stabilize. MODE. Control input MODE is used to toggle between fast decay mode and slow decay mode. A logic high puts the device in slow decay mode. Synchronous rectification is always enabled. Braking. The braking function is implemented by driving the device in slow decay mode via the MODE setting and applying an enable chop command. Because it is possible to drive current in both directions through the DMOS switches, this configuration effectively shorts out the motor generated BEMF as long as the ENABLE chop mode is asserted. The maximum current can be approximated by VBEMF/RL. Care should be taken to insure that the maximum ratings of the device are not exceeded in worse case braking situations: high speed and high-inertia loads. Diagnostic Output. The NFAULT pin signals a problem with the chip via an open drain output. A motor fault, undervoltage condition, or TJ > 160C will drive the pin active low. This output is not valid when SLEEP puts the device into minimum power dissipation mode. TSD. Two die temperature monitors are integrated on the chip. As die temperature increases towards the maximum, a thermal warning signal will be triggered at 160C. This fault drives the NFAULT low, but does not disable the operation of the chip. If the die temperature increases further, to approximately 175C, the full-bridge outputs will be disabled until the internal temperature falls below a hysteresis of 15C.
ENABLE 1 1 0 0 0 X
MODE X X 1 0 0 X
SLEEP 1 1 1 1 1 0
OUTA H L L L H Z
OUTB L H L H L Z Forward Reverse
Function
Brake (slow decay) Fast Decay Synchronous Rectification2 Fast Decay Synchronous Rectification2 Sleep Mode
indicates "don't care," Z indicates high impedance. prevent reversal of current during fast decay synchronous rectification, outputs go to the high impedance state as the current approaches 0 A.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
7
A3950
DMOS Full-Bridge Motor Driver
Overcurrent Protection. Referring to the figures below, the voltage on the output pins relative to supply are monitored to ensure that the motor lead is not shorted to supply or ground. If a short is detected, the full-bridge outputs are turned off, flag NFAULT is driven low, and a 1.2 ms fault timer is started.
After this 1.2 ms period, tOCP , the device will then be allowed to follow the input commands and another turn-on is attempted. If there is still a fault condition, the cycle repeats. If, after tOCP expires, it is determined that the short condition is not present, the NFAULT pin is released and normal operation resumes.
2 s / div. 2 A / div.
ISHORT
Fault asserted NFAULT
Shorted load condition, output current waveform is shown along with the NFAULT output.
TOCP = 1.2 ms
200 s / div. 2 A / div.
ISHORT
Fault asserted NFAULT
Shorted load condition illustrating repetitive cycles with a 1.2 ms delay.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
8
A3950
DMOS Full-Bridge Motor Driver
Applications Information
Power Dissipation. First order approximation of power dissipation in the A3950 can be calculated by first examining the power dissipation in the full-bridge during each of the operation modes. The A3950 features synchronous rectification, a feature that effectively shorts out the body diode by turning on the low RDS(on) DMOS driver during the decay cycle. This significantly reduces power dissipation in the full-bridge. In order to prevent shoot-through, where both
source and sink driver are on at the same time, the A3950 implements a 500 ns typical crossover delay time. For this period, the body diode in the decay current path conducts the current until the DMOS driver turns on. This does affect power dissipation and should be considered in high current, high ambient temperature applications. In addition, motor parameters and switching losses can add power dissipation that could affect critical applications. Drive Current. This current path is through source DMOS driver, motor winding, and sink DMOS driver. Power dissipation is I2R loses in one source and one sink DMOS driver, as shown in the following equation:
VBB
PD = I 2 ( RDS(on)Source + RDS(on)Sink )
1
(1)
3 2
Fast Decay with Synchronous Rectification. This decay mode is equivalent to a phase change where the opposite drivers are switched on. When in fast decay, the motor current is not allowed to go negative (direction change). Instead, as the current approaches zero, the drivers turn off. The power calculation is the same as the drive current calculation, equation 1: Slow Decay SR (Brake Mode). In this decay mode, both sink drivers turn on, allowing the current to circulate through the sink drivers and the load. Power dissipation is I2R loses in the two sink DMOS drivers:
1 Drive current 2 Fast decay with synchronous rectification (reverse) 3 Slow decay with synchronous rectification (brake)
Figure 1. Current Decay Patterns
PD = I 2 ( 2 x RDS(on)Sink )
(2)
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
9
A3950
DMOS Full-Bridge Motor Driver
SENSE Pin. A low value resistor can be placed between the SENSE pin and ground for current sensing purposes. To minimize ground-trace IR drops in sensing the output current level, the current sensing resistor should have an independent ground return to the star ground point. This trace should be as short as possible. For low value sense resistors, the IR drops in the PCB can be significant, and should be taken into account. When selecting a value for the sense resistor be sure not to exceed the maximum voltage on the SENSE pin of 500 mV. Ground. A star ground should be located as close to the A3950 as possible. The copper ground plane directly under the exposed thermal pad makes a good location for the star ground point. The exposed pad can be connected to ground for this purpose.
Layout. The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A3950 must be soldered directly onto the board. On the underside of the A3950 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. The load supply pin, VBB, should be decoupled with an electrolytic capacitor (typically 100 F) in parallel with a ceramic capacitor placed as close as possible to the device. The ceramic capacitors between VCP and VBB, connected to VREG, and between CP1 and CP2, should be as close to the pins of the device as possible, in order to minimize lead inductance.
VBB C1
NFAULT MODE VREG C1 C2
VBB
VCP
C2 U1 GND C3
CVBB1
PHASE GND SLEEP ENABLE
CVBB1 GND CP2 CP1 OUTB C3
A3950 EU Package
PAD
SENSE
OUTA
CVBB2
GND
CVBB2
OUTA
OUTB
EU package shown
VBB
NC
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
10
A3950
DMOS Full-Bridge Motor Driver
EU Package, 16 Pin QFN with Exposed Thermal Pad
All dimensions reference only, not for tooling use. (reference JEDEC MO-220WGGC-4) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN65P400X400X80-17BM); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 16X 0.08 [.003] C 0.35 .014 16X 0.25 .010
4.15 .163 3.85 .152 16 A
A B
1 2
4.15 .163 3.85 .152
SEATING PLANE 0.80 .031 0.70 .028 0.20 .008 REF 0.05 .002 0.00 .000
C
0.10 [.004] M C A B 0.05 [.002] M C 0.65 .026 0.35 .014 NOM 16 0.65 .026 NOM 0.65 .026 0.45 .018
1.15 .045 NOM
1 4X0.20 .008 MIN 2
C 3.8 .150 NOM 0.15R .006 REF 2 1
B
2.15 .085 NOM
12X0.20 .008 MIN
2.15 .085 NOM 4X 0.20 .008 MIN
16 2.15 .085 NOM
2.15 .085 NOM 3.8 .150 NOM
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
11
A3950
DMOS Full-Bridge Motor Driver
LP Package, 16 Pin TSSOP with Exposed Thermal Pad
16
5.10 .201 4.90 .193
A B
8 0 0.20 .008 0.09 .004
B 3 .118 NOM A
4.5 4.3
.177 .169 6.6 6.2 .260 .244
0.75 .030 0.45 .018 1 .039 REF
1
2
3 .118 NOM C
0.25 .010 SEATING PLANE 1.20 .047 MAX SEATING PLANE GAUGE PLANE
16X 0.10 [.004] C 16X 0.30 .012 0.19 .007 0.10 [.004] M C A B 0.65 .026 14X0.20 .008 MIN 16
0.15 .006 0.00 .000
0.45 .018 NOM 1.65 .065 NOM
0.65 .026 NOM All dimensions reference only, not for tooling use. (reference JEDEC MO-153 ABT) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) U.S. Customary dimensions controlling C Reference land pattern layout (reference IPC7351 TSOP65P640X120-17M); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
2X0.20 .008 MIN
C
3 .118 NOM
6.1 .240 NOM
12 3 .118 NOM
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copyright(c)2005, 2006 Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
12

▲Up To Search▲

Price & Availability of A395006

	To Download A395006 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .